Zhu Zhenhua

Zhenhua Zhu is an Assistant Professor at Tsinghua Shenzhen International Graduate School(SIGS). His research focuses on high-efficiency AI chip architectures and systems, with interests spanning processing-in-memory/near-memory computing, supernode AI computing systems, and space AI computing chips and systems. He is committed to developing architectural design methodologies and tools for overcoming the “memory wall” and “power wall” bottlenecks. As first author or corresponding author, he has published more than 20 papers in leading conferences and journals, including IEEE TCAD, ISCA, MICRO, HPCA, DAC, and ICCAD, with over 2,100 Google Scholar citations.

Zhenhua Zhu received his Ph.D. and B.S. degrees from the Department of Electronic Engineering, Tsinghua University, in 2024 and 2018, respectively. He has received the CCF Fault-Tolerant Computing Technical Committee 40th Anniversary Outstanding Achievement Award(the first contributor); the 2025 Best Paper Award and Most Influential Paper Award of the Journal of Electronics & Information Technology; the HPCA 2025 Best Paper Honorable Mention; the DATE 2023 Best Paper Nomination; the Outstanding Ph.D. Graduate Award of Tsinghua University; and the Outstanding Ph.D. Dissertation Award of Tsinghua University. He was selected for the Shuimu Tsinghua Scholar Program and the Chuanxin Scholar Program of the Department of Electronic Engineering, Tsinghua University. He serves as the Principal Investigator of a National Natural Science Foundation of China Young Scientists Fund (Category C) project.

2018.08-2024.01  Tsinghua University  Electronic Science and TechnologyPhD

2014.08-2018.08  Tsinghua University  Electronic Engineering   Bachelor

2026.06-Now    Tsinghua University   Assistant Professor

2024.03-2026.05   Tsinghua University   Postdoctoral Assistant Researcher

2024.07-2026.06   HKUST     Visiting Scholar

Asia and South Pacific Design Automation Conference 2025（ASP-DAC 2025）技术委员会秘书(Technical Program Committee Secretary)；

国际会议技术委员会委员(Technical Program Committee Member)：

IEEE/ACM International Conference on Computer-Aided Design（ICCAD）

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems（CASES）

Great Lakes Symposium on VLSI（GLSVLSI）

IEEE Computer Society Annual Symposium on VLSI（ISVLSI）

国际期刊审稿人(Journal Reviewer)：

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（IEEE TCAD）

ACM Transactions on Design Automation of Electronic Systems（ACM TODAES）

ACM Transactions on Embedded Computing Systems（ACM TECS）

Zhenhua Zhu’s research focuses on high-efficiency AI chip architectures and systems, with research interests spanning processing-in-memory and near-memory computing, supernode AI computing systems, and space AI computing chips and systems. Targeting large models and data-intensive applications, he studies novel computing architectures and system optimization methodologies. His work covers processing-in-memory, 3D-stacked near-memory computing, heterogeneous supernode AI computing systems, architectural performance modeling, compilation and mapping optimization, and design-space exploration. These efforts aim to establish cross-layer co-optimization methodologies considering device and circuit characteristics, computing architectures, compilation tools, and system deployment, and further extend toward high-efficiency and high-reliability intelligent computing chips and systems for spaceenvironments. He serves as the Principal Investigator of a National Natural Science Foundation of China(NSFC) Young Scientists Fund (Category C) project and several university-industry collaborative projects, and has participatedas a key contributor in projects ofNSFC key program and National Key Research and Development Program of China. His research has received multiple best paper awards and nominations at leading journals and conferences.

1. Research on Processing-In-Memory Architecture and Scheduling Methods for Multimodal Self-Learning Embodied Intelligence, NSFC Youth Funding (Category-C) 国家自然科学基金青年科学基金项目（C类），2026.01-2028.12，30万元，项目负责人(PI)；
2. 面向AI智能体的HBF-DRAM存算一体协同架构的层次化存储管理与优化研究 (Hierarchical Memory Management and Optimization for an HBF-DRAM Processing-in-Memory Architecture Oriented to AI Agents), 清华大学-杭州知存算力科技有限公司“多模态智能感存算融合系统”产学研深度融合专项 (Tsinghua University-Hangzhou Witmem Computing Power Technology Co., Ltd. “Multimodal Intelligent Sensing-Computing Fusion System” Industry-Academia-Research Deep Integration Project), 2026.01-2026.12, 100万元，项目负责人(PI)；
3. 面向大模型的异构融合端侧存算一体芯片与系统 (Heterogeneous Integrated Edge-side Processing-in-Memory Chips and Systems for Large Models)，北京市自然科学基金 (Beijing Natural Science Foundation)，2025.07-2027.06，300万元，项目主要参与成员(Key Contributor)。

4. 存算一体高层次设计自动化工具 (High-Level Synthesis for Processing-In-Memory AI Chips and Architecture), 科技部重点研发计划 (National Key R&D Program of China), 2023-2027, 650万元，项目主要参与人员 (Key Contributor)。

[1] Tongxin Xie, Mingyu Gao, Zehao Wang, Zhihao Jia, Yuechen Xi, Bing Li, Mo Guang, Jiale Yan, Kaiwen Long, Xingcheng Zhang, Huazhong Yang, Yuan Xie, Zhenhua Zhu, and Yu Wang, Bringing Near Data Processing into the Low-Bit Floating-Point Era, in the 53rd Annual International Symposium on Computer Architecture, IEEE/ACM, 2026: 1383-1399.

[2] Tongxin Xie, Zhenhua Zhu, Bing Li, Yukai He, Cong Li, Guangyu Sun, Huazhong Yang, Yuan Xie, Yu Wang, UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures, 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2025: 624-640.

[3] Hongyi Wang, Zhenhua Zhu, Tianchen Zhao, Yunfei Xiang, Zehao Wang, Jincheng Yu, Huazhong Yang, Yuan Xie and Yu Wang. REACT3D: Real-time Edge Accelerator for Incremental Training in 3D Gaussian Splatting based SLAM Systems, Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture. 2025: 1852-1866.

[4] Lidong Guo, Zhenhua Zhu, Qiushi Lin, Yuan Xie, Huazhong Yang, Wangyang Fu, and Yu Wang. How Do Errors Impact NN Accuracy on Non-Ideal Analog PIM? Fast Evaluation via an Error-Injected Robustness Metric, 2025 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2025: 1-9.

[5] Shuai Yuan, Angxin Cai, Qiushi Lin, Guoxing Wang, Yu Wang, Zhenhua Zhu, and Yanan Sun. HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs, 2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025: 1-7.

[6] Lidong Guo, Zhenhua Zhu, Tengxuan Liu, Xuefei Ning, Shiyao Li, Guohao Dai, Huazhong Yang, Wangyang Fu, and Yu Wang. Towards floating point-based attention-free LLM: Hybrid PIM with non-uniform data format and reduced multiplications, Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design. 2024: 1-9.

[7] Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, X. Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, Yu Wang. MNSIM 2.0: A behavior-level modeling tool for processing-in-memory architectures. IEEE transactions on computer-aided design of integrated circuits and systems, 2023, 42(11): 4112-4125.

[8] Zhenhua Zhu, Jun Liu, Guohao Dai, Shulin Zeng, Bing Li, Huazhong Yang and Yu Wang. Processing-in-hierarchical-memory architecture for billion-scale approximate nearest neighbor search[C]//2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE, 2023: 1-6.

[9] Zhenhua Zhu, Hanbo Sun, Yujun Lin, Guohao Dai, Lixue Xia, Song Han, Yu Wang, Huazhong Yang. A configurable multi-precision CNN computing framework based on single bit RRAM, Proceedings of the 56th Annual Design Automation Conference 2019. 2019: 1-6.

[10] Zhenhua Zhu, Jilan Lin, Ming Cheng, Lixue Xia, Hanbo Sun, Xiaoming Chen, Yu Wang and Huazhong Yang. Mixed size crossbar-based RRAM CNN accelerator with overlapped mapping method[C]//Proceedings of the International Conference on Computer-Aided Design. 2018: 1-8

1. 一种基于存内计算的图卷积网络软硬件协同加速方法，CN114707648B，汪玉、朱昱、朱振华、戴国浩、杨华中

    A Software-Hardware Co-Design Acceleration Method for Graph Convolutional Networks Based on Processing-in-Memory, CN114707648B, Yu Wang, Yu Zhu, Zhenhua Zhu, Guohao Dai, Huazhong Yang

2. 基于非易失器件的通用逻辑综合方法及装置，CN110765710B，刘家隆、马铭远、朱振华、汪玉、杨华中

    A General Logic Synthesis Method and Apparatus Based on Non-Volatile Devices, CN110765710B, Jialong Liu, Mingyuan Ma, Zhenhua Zhu, Yu Wang, Huazhong Yang

3. 数据处理装置的控制方法与装置，CN116991910B，戴国浩、朱振华、汪玉、肖世海、傅天予、张学仓

    Control Method and Apparatus for a Data Processing Device, CN116991910B, Guohao Dai, Zhenhua Zhu, Yu Wang, Shihai Xiao, Tianyu Fu, Xuecang Zhang

4. 面向近存储计算架构的编译方法和系统、电子设备与存储介质，CN120144134A，汪玉、谢童欣、朱振华

    Compilation Method and System for Near-Memory Computing Architectures, Electronic Device, and Storage Medium, CN120144134A, Yu Wang, Tongxin Xie, Zhenhua Zhu

5. 神经网络的算子融合策略的确定方法、装置及存储介质，CN119312883B，汪玉、王鸿懿、朱振华、曾书霖

    Method, Apparatus, and Storage Medium for Determining an Operator Fusion Strategy for Neural Networks, CN119312883B, Yu Wang, Hongyi Wang, Zhenhua Zhu, Shulin Zeng

The CCF Fault-Tolerant Computing Technical Committee 40th Anniversary Outstanding Achievement Award

2025 Best Paper Award and Most Influential Paper Award of the Journal of Electronics & Information Technology

HPCA 2025 Best Paper Honorable Mention

DATE 2023 Best Paper Nomination

Outstanding Ph.D. Graduate Award of Tsinghua University

 Outstanding Ph.D. Dissertation Award of Tsinghua University